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-rw-r--r--part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do9
-rw-r--r--part_2/ex5/simulation/modelsim/tb_counter.do9
2 files changed, 18 insertions, 0 deletions
diff --git a/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do b/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do
new file mode 100644
index 0000000..98180fe
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/VERI/part_2/ex5 {C:/VERI/part_2/ex5/counter_8.v}
+
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
new file mode 100644
index 0000000..245fe11
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -0,0 +1,9 @@
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
+run 100ns \ No newline at end of file