diff options
Diffstat (limited to 'part_2/ex9')
| -rw-r--r-- | part_2/ex9/add3_ge5.v | 11 | ||||
| -rw-r--r-- | part_2/ex9/bin2bcd_16.v | 97 | ||||
| -rw-r--r-- | part_2/ex9/counter_16.v | 25 | ||||
| -rw-r--r-- | part_2/ex9/delay.v | 26 | ||||
| -rw-r--r-- | part_2/ex9/divider_2500.v | 36 | ||||
| -rw-r--r-- | part_2/ex9/divider_50000.v | 31 | ||||
| -rw-r--r-- | part_2/ex9/ex9_top.v | 50 | ||||
| -rw-r--r-- | part_2/ex9/fsm.v | 245 | ||||
| -rw-r--r-- | part_2/ex9/hex_to_7seg.v | 28 | ||||
| -rw-r--r-- | part_2/ex9/lsfr.v | 14 | ||||
| -rw-r--r-- | part_2/ex9/timer.v | 18 |
11 files changed, 581 insertions, 0 deletions
diff --git a/part_2/ex9/add3_ge5.v b/part_2/ex9/add3_ge5.v new file mode 100644 index 0000000..282dcac --- /dev/null +++ b/part_2/ex9/add3_ge5.v @@ -0,0 +1,11 @@ +module add3_ge5 (in,out);
+
+ input [3:0] in;
+ output reg [3:0] out;
+
+ always @ (in)
+ if (in >= 4'd5)
+ out <= in + 4'd3;
+ else
+ out <= in;
+endmodule
\ No newline at end of file diff --git a/part_2/ex9/bin2bcd_16.v b/part_2/ex9/bin2bcd_16.v new file mode 100644 index 0000000..fdfb655 --- /dev/null +++ b/part_2/ex9/bin2bcd_16.v @@ -0,0 +1,97 @@ +//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+// .... it uses a shift-and-add3 algorithm
+// Creator: Peter Cheung
+// Version: 1.0
+// Date: 18 Sept 2016
+//------------------------------
+// For more explanation of how this work, see
+// ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+ input [15:0] B; // binary input number
+ output [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4; // BCD digit LSD to MSD
+
+ wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+ wire [3:0] w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+ wire [3:0] w26,w27,w28,w29;
+ wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+ wire [3:0] a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+ wire [3:0] a26,a27,a28,a29;
+
+ // Instantiate a tree of add3-if-greater than or equal to 5 cells
+ // ... input is w_n, and output is a_n
+ add3_ge5 A1 (w1,a1);
+ add3_ge5 A2 (w2,a2);
+ add3_ge5 A3 (w3,a3);
+ add3_ge5 A4 (w4,a4);
+ add3_ge5 A5 (w5,a5);
+ add3_ge5 A6 (w6,a6);
+ add3_ge5 A7 (w7,a7);
+ add3_ge5 A8 (w8,a8);
+ add3_ge5 A9 (w9,a9);
+ add3_ge5 A10 (w10,a10);
+ add3_ge5 A11 (w11,a11);
+ add3_ge5 A12 (w12,a12);
+ add3_ge5 A13 (w13,a13);
+ add3_ge5 A14 (w14,a14);
+ add3_ge5 A15 (w15,a15);
+ add3_ge5 A16 (w16,a16);
+ add3_ge5 A17 (w17,a17);
+ add3_ge5 A18 (w18,a18);
+ add3_ge5 A19 (w19,a19);
+ add3_ge5 A20 (w20,a20);
+ add3_ge5 A21 (w21,a21);
+ add3_ge5 A22 (w22,a22);
+ add3_ge5 A23 (w23,a23);
+ add3_ge5 A24 (w24,a24);
+ add3_ge5 A25 (w25,a25);
+ add3_ge5 A26 (w26,a26);
+ add3_ge5 A27 (w27,a27);
+ add3_ge5 A28 (w28,a28);
+ add3_ge5 A29 (w29,a29);
+
+ // wire the tree of add3 modules together
+ assign w1 = {B[14:11]}; // wn is the input port to module An
+ assign w2 = {a1[2:0], B[10]};
+ assign w3 = {1'b0, B[15], a1[3], a2[3]};
+ assign w4 = {a2[2:0], B[9]};
+ assign w5 = {a3[2:0], a4[3]};
+ assign w6 = {a4[2:0], B[8]};
+ assign w7 = {a5[2:0], a6[3]};
+ assign w8 = {a6[2:0], B[7]};
+ assign w9 = {1'b0, a3[3], a5[3], a7[3]};
+ assign w10 = {a7[2:0], a8[3]};
+ assign w11 = {a8[2:0], B[6]};
+ assign w12 = {a9[2:0], a10[3]};
+ assign w13 = {a10[2:0], a11[3]};
+ assign w14 = {a11[2:0], B[5]};
+ assign w15 = {a12[2:0], a13[3]};
+ assign w16 = {a13[2:0], a14[3]};
+ assign w17 = {a14[2:0], B[4]};
+ assign w18 = {1'b0, a9[3], a12[3], a15[3]};
+ assign w19 = {a15[2:0], a16[3]};
+ assign w20 = {a16[2:0], a17[3]};
+ assign w21 = {a17[2:0], B[3]};
+ assign w22 = {a18[2:0], a19[3]};
+ assign w23 = {a19[2:0], a20[3]};
+ assign w24 = {a20[2:0], a21[3]};
+ assign w25 = {a21[2:0], B[2]};
+ assign w26 = {a22[2:0], a23[3]};
+ assign w27 = {a23[2:0], a24[3]};
+ assign w28 = {a24[2:0], a25[3]};
+ assign w29 = {a25[2:0], B[1]};
+
+ // connect up to four BCD digit outputs
+ assign BCD_0 = {a29[2:0],B[0]};
+ assign BCD_1 = {a28[2:0],a29[3]};
+ assign BCD_2 = {a27[2:0],a28[3]};
+ assign BCD_3 = {a26[2:0],a27[3]};
+ assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};
+endmodule
+
+
+
+
diff --git a/part_2/ex9/counter_16.v b/part_2/ex9/counter_16.v new file mode 100644 index 0000000..8343c18 --- /dev/null +++ b/part_2/ex9/counter_16.v @@ -0,0 +1,25 @@ +`timescale 1ns / 100ps
+
+
+module counter_16 (
+ clock,
+ enable,
+ count,
+ reset
+ );
+
+ parameter BIT_SZ = 16;
+ input clock;
+ input enable;
+ input reset;
+ output reg [BIT_SZ-1:0] count;
+
+
+ initial count = 0;
+
+ always @ (posedge clock)
+ if (reset == 1'b0)
+ count <= 0;
+ else if (enable == 1'b0)
+ count <= count + 1'b1;
+endmodule
diff --git a/part_2/ex9/delay.v b/part_2/ex9/delay.v new file mode 100644 index 0000000..71bee21 --- /dev/null +++ b/part_2/ex9/delay.v @@ -0,0 +1,26 @@ +module delay(
+ input CLOCK,
+ input [13:0] DELAY,
+ input START_DELAY,
+ output reg TIME_OUT
+);
+ reg [13:0] COUNT;
+
+ always @ (posedge CLOCK)
+ begin
+ if (START_DELAY == 1'b1)
+ begin
+ if (COUNT < DELAY+14'd24)
+ begin
+ COUNT <= COUNT + 1'b1;
+ TIME_OUT <= 1'b0;
+ end
+ else
+ begin
+ COUNT <= 0;
+ TIME_OUT <= 1'b1;
+ end
+ end
+
+ end
+endmodule
diff --git a/part_2/ex9/divider_2500.v b/part_2/ex9/divider_2500.v new file mode 100644 index 0000000..305b2b6 --- /dev/null +++ b/part_2/ex9/divider_2500.v @@ -0,0 +1,36 @@ +`timescale 1ns / 100ps
+
+
+module divider_2500 (
+ clock,
+ clock_ms,
+ out
+ );
+
+ parameter BIT_SZ = 12;
+ input clock;
+ input clock_ms;
+ reg [BIT_SZ-1:0] count;
+
+ initial count = 0;
+
+ output reg out;
+
+
+ always @ (posedge clock)
+ begin
+ if (clock_ms)
+ begin
+ if (count < 12'd499)
+ begin
+ count <= count + 1'b1;
+ out <= 1'b0;
+ end
+ else
+ begin
+ out <= 1'b1;
+ count <= 1'b0;
+ end
+ end
+ end
+endmodule
diff --git a/part_2/ex9/divider_50000.v b/part_2/ex9/divider_50000.v new file mode 100644 index 0000000..d50d5b0 --- /dev/null +++ b/part_2/ex9/divider_50000.v @@ -0,0 +1,31 @@ +`timescale 1ns / 100ps
+
+
+module divider_50000 (
+ clock,
+ out
+ );
+
+ parameter BIT_SZ = 16;
+ input clock;
+ reg [BIT_SZ-1:0] count;
+
+ initial count = 0;
+
+ output reg out;
+
+
+ always @ (posedge clock)
+ begin
+ if (count < 16'd49999)
+ begin
+ count <= count + 1'b1;
+ out <= 1'b0;
+ end
+ else
+ begin
+ out <= 1'b1;
+ count <= 1'b0;
+ end
+ end
+endmodule
diff --git a/part_2/ex9/ex9_top.v b/part_2/ex9/ex9_top.v new file mode 100644 index 0000000..b894df2 --- /dev/null +++ b/part_2/ex9/ex9_top.v @@ -0,0 +1,50 @@ +module ex9_top (
+ input CLOCK_50,
+
+ input [3:0] KEY,
+
+ output [6:0] HEX0,
+ output [6:0] HEX1,
+ output [6:0] HEX2,
+ output [6:0] HEX3,
+ output [6:0] HEX4,
+ output [9:0] LEDR
+);
+ // Define 1ms and 0.5s (half-second)
+ wire CLOCK_MS;
+ wire CLOCK_HS;
+
+ wire [15:0] B;
+ wire [3:0] BCD_0;
+ wire [3:0] BCD_1;
+ wire [3:0] BCD_2;
+ wire [3:0] BCD_3;
+ wire [3:0] BCD_4;
+
+ wire TIME_OUT;
+ wire START_DELAY;
+ wire EN_LFSR;
+ wire [13:0] PRBS;
+ wire COUNT;
+ wire [15:0] TIME;
+ wire COUNT_CLEAR;
+
+ divider_50000 DIV0 (CLOCK_50, CLOCK_MS);
+ divider_2500 DIV1 (CLOCK_50, CLOCK_MS, CLOCK_HS);
+
+ fsm FSM0 (CLOCK_MS, CLOCK_HS, KEY[3], TIME_OUT, START_DELAY, EN_LFSR, LEDR, COUNT, COUNT_CLEAR);
+
+ delay DELAY0 (CLOCK_MS, PRBS, START_DELAY, TIME_OUT);
+
+ lfsr LSFR0 (CLOCK_MS, EN_LFSR, PRBS);
+
+ timer TIME0 (CLOCK_MS, COUNT, COUNT_CLEAR, TIME);
+
+ bin2bcd_16 BIN0 (TIME, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+ hex_to_7seg SEG0 (HEX0,BCD_0);
+ hex_to_7seg SEG1 (HEX1,BCD_1);
+ hex_to_7seg SEG2 (HEX2,BCD_2);
+ hex_to_7seg SEG3 (HEX3,BCD_3);
+ hex_to_7seg SEG4 (HEX4,BCD_4);
+endmodule
diff --git a/part_2/ex9/fsm.v b/part_2/ex9/fsm.v new file mode 100644 index 0000000..2e3888a --- /dev/null +++ b/part_2/ex9/fsm.v @@ -0,0 +1,245 @@ +module fsm(
+ input CLOCK_MS,
+ input CLOCK_HS,
+
+ input KEY,
+ input TIME_OUT,
+
+ output reg START_DELAY,
+ output reg EN_LFSR,
+ output reg [9:0] LEDR,
+ output reg COUNT,
+ output reg COUNT_CLEAR
+);
+ reg [3:0] state;
+
+ parameter wait_key_press=0, wait_key_release=1, led_one=2, led_two=3, led_three=4, led_four=5, led_five=6, led_six=7, led_seven=8, led_eight=9, led_nine=10, led_ten=11, delay=12, led_zero=13, response=14, response_end=15;
+
+ always @ (state)
+ begin
+ case (state)
+ wait_key_press:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b0;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ wait_key_release:
+ begin
+ EN_LFSR <= 1'b1;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b0;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b1;
+ end
+ led_zero:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b0;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_one:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1000000000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_two:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1100000000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_three:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1110000000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_four:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111000000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_five:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111100000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_six:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111110000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_seven:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111111000;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_eight:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111111100;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_nine:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111111110;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ led_ten:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b1111111111;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ delay:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b1;
+ LEDR [9:0] <= 10'b1111111111;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ response:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b1;
+ LEDR [9:0] <= 10'b0;
+ COUNT <= 1'b1;
+ COUNT_CLEAR <= 1'b0;
+ end
+ response_end:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b0;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ default:
+ begin
+ EN_LFSR <= 1'b0;
+ START_DELAY <= 1'b0;
+ LEDR [9:0] <= 10'b0;
+ COUNT <= 1'b0;
+ COUNT_CLEAR <= 1'b0;
+ end
+ endcase
+ end
+
+ always @(posedge CLOCK_MS)
+ begin
+ case (state)
+ wait_key_press:
+ if (~KEY)
+ state = wait_key_release;
+ else
+ state = wait_key_press;
+ wait_key_release:
+ if (KEY)
+ state = led_zero;
+ else
+ state = wait_key_release;
+ led_zero:
+ if (CLOCK_HS)
+ state = led_one;
+ else
+ state = led_zero;
+ led_one:
+ if (CLOCK_HS)
+ state = led_two;
+ else
+ state = led_one;
+ led_two:
+ if (CLOCK_HS)
+ state = led_three;
+ else
+ state = led_two;
+ led_three:
+ if (CLOCK_HS)
+ state = led_four;
+ else
+ state = led_three;
+ led_four:
+ if (CLOCK_HS)
+ state = led_five;
+ else
+ state = led_four;
+ led_five:
+ if (CLOCK_HS)
+ state = led_six;
+ else
+ state = led_five;
+ led_six:
+ if (CLOCK_HS)
+ state = led_seven;
+ else
+ state = led_six;
+ led_seven:
+ if (CLOCK_HS)
+ state = led_eight;
+ else
+ state = led_seven;
+ led_eight:
+ if (CLOCK_HS)
+ state = led_nine;
+ else
+ state = led_eight;
+ led_nine:
+ if (CLOCK_HS)
+ state = led_ten;
+ else
+ state = led_nine;
+ led_ten:
+ if (CLOCK_HS)
+ state = delay;
+ else
+ state = led_ten;
+ delay:
+ if (TIME_OUT)
+ state = response;
+ else
+ state = delay;
+ response:
+ if (~KEY)
+ state = response_end;
+ else
+ state = response;
+ response_end:
+ if (KEY)
+ state = wait_key_press;
+ else
+ state = response_end;
+ endcase
+ end
+endmodule
diff --git a/part_2/ex9/hex_to_7seg.v b/part_2/ex9/hex_to_7seg.v new file mode 100644 index 0000000..6b476e3 --- /dev/null +++ b/part_2/ex9/hex_to_7seg.v @@ -0,0 +1,28 @@ +module hex_to_7seg (out,in);
+ output [6:0] out;
+ input [3:0] in;
+
+ reg [6:0] out;
+
+ always @ (*)
+ case (in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000010;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'hA: out = 7'b0001000;
+ 4'hB: out = 7'b0000011;
+ 4'hC: out = 7'b1000110;
+ 4'hD: out = 7'b0100001;
+ 4'hE: out = 7'b0000110;
+ 4'hF: out = 7'b0001110;
+ endcase
+endmodule
+
+
\ No newline at end of file diff --git a/part_2/ex9/lsfr.v b/part_2/ex9/lsfr.v new file mode 100644 index 0000000..44e931c --- /dev/null +++ b/part_2/ex9/lsfr.v @@ -0,0 +1,14 @@ +module lfsr(
+ input CLOCK,
+ input ENABLE,
+ output reg [13:0] SHIFT
+);
+
+ initial SHIFT = 13'd1;
+
+ always @ (posedge CLOCK)
+ begin
+ if (ENABLE == 1'b1)
+ SHIFT <= {SHIFT[12:0],(SHIFT[13] ^ SHIFT[11]) ^ SHIFT[3]};
+ end
+endmodule
diff --git a/part_2/ex9/timer.v b/part_2/ex9/timer.v new file mode 100644 index 0000000..4974ca2 --- /dev/null +++ b/part_2/ex9/timer.v @@ -0,0 +1,18 @@ +`timescale 1ns / 100ps
+
+
+module timer (
+ input clock,
+ input count,
+ input count_clear,
+ output reg [15:0] tim
+ );
+
+ always @ (posedge clock)
+ begin
+ if (count_clear)
+ tim <= 0;
+ else if (count)
+ tim <= tim + 16'b1;
+ end
+endmodule
|