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-rw-r--r--part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do9
1 files changed, 9 insertions, 0 deletions
diff --git a/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do b/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do
new file mode 100644
index 0000000..7c53536
--- /dev/null
+++ b/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/VERI/part_3/ex10a {C:/VERI/part_3/ex10a/spi2dac.v}
+