part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do


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if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+C:/VERI/part_3/ex10a {C:/VERI/part_3/ex10a/spi2dac.v}