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IC-EE2 Verilog Laboratory
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part_3
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ex10
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simulation
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modelsim
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spitest.do
blob: 639e10bda7e3d9092953b4e43c601434c3228877 (
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)
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add wave SW force SW
2
#
001000111101
force clock
0
0
,
1
10ns
-
repeat 20ns
run
100ns