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authorVasil Zlatanov <vasil.zlatanov@gmail.com>2016-12-13 19:55:32 +0000
committerVasil Zlatanov <vasil.zlatanov@gmail.com>2016-12-13 19:55:32 +0000
commit45986d7b591729e41eac316383553f34728d12d3 (patch)
tree0dc98b06f9d5a9be4f4602e9d3a9536f640028b2
parent4b6e0102d20d9ab060ce930e4b846c8be446bb06 (diff)
downloade2-verilab-45986d7b591729e41eac316383553f34728d12d3.tar.gz
e2-verilab-45986d7b591729e41eac316383553f34728d12d3.tar.bz2
e2-verilab-45986d7b591729e41eac316383553f34728d12d3.zip
fix wrong overcorrection in index
-rw-r--r--part_2/ex9/divider_2500.v2
-rw-r--r--part_2/ex9/divider_50000.v2
2 files changed, 2 insertions, 2 deletions
diff --git a/part_2/ex9/divider_2500.v b/part_2/ex9/divider_2500.v
index 305b2b6..f4322b7 100644
--- a/part_2/ex9/divider_2500.v
+++ b/part_2/ex9/divider_2500.v
@@ -21,7 +21,7 @@ module divider_2500 (
begin
if (clock_ms)
begin
- if (count < 12'd499)
+ if (count < 12'd500)
begin
count <= count + 1'b1;
out <= 1'b0;
diff --git a/part_2/ex9/divider_50000.v b/part_2/ex9/divider_50000.v
index d50d5b0..6ce09f9 100644
--- a/part_2/ex9/divider_50000.v
+++ b/part_2/ex9/divider_50000.v
@@ -17,7 +17,7 @@ module divider_50000 (
always @ (posedge clock)
begin
- if (count < 16'd49999)
+ if (count < 16'd50000)
begin
count <= count + 1'b1;
out <= 1'b0;