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authorVasil Zlatanov <v@skozl.com>2016-12-12 21:51:10 +0000
committerVasil Zlatanov <v@skozl.com>2016-12-12 21:51:10 +0000
commit4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch)
treee475eab3716738f2928f0b2063956e9b155f94ab /part_2/ex5
downloade2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz
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public push
Diffstat (limited to 'part_2/ex5')
-rw-r--r--part_2/ex5/counter_8.v22
-rw-r--r--part_2/ex5/ex5_top_nativelink_simulation.rpt21
-rw-r--r--part_2/ex5/output_files/ex5_top.flow.rpt118
-rw-r--r--part_2/ex5/output_files/ex5_top.map.rpt298
-rw-r--r--part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do9
-rw-r--r--part_2/ex5/simulation/modelsim/tb_counter.do9
6 files changed, 477 insertions, 0 deletions
diff --git a/part_2/ex5/counter_8.v b/part_2/ex5/counter_8.v
new file mode 100644
index 0000000..84052fc
--- /dev/null
+++ b/part_2/ex5/counter_8.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps
+
+
+module counter_8 (
+ clock,
+ enable,
+ count
+ );
+
+ parameter BIT_SZ = 8;
+ input clock;
+ input enable;
+ output [BIT_SZ-1:0] count;
+
+ reg[BIT_SZ-1:0] count;
+
+ initial count = 0;
+
+ always @ (posedge clock)
+ if (enable == 1'b1)
+ count <= count + 1'b1;
+endmodule
diff --git a/part_2/ex5/ex5_top_nativelink_simulation.rpt b/part_2/ex5/ex5_top_nativelink_simulation.rpt
new file mode 100644
index 0000000..833b429
--- /dev/null
+++ b/part_2/ex5/ex5_top_nativelink_simulation.rpt
@@ -0,0 +1,21 @@
+Info: Start Nativelink Simulation process
+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
+
+========= EDA Simulation Settings =====================
+
+Sim Mode : RTL
+Family : cyclonev
+Quartus root : c:/altera/16.0/quartus/bin64/
+Quartus sim root : c:/altera/16.0/quartus/eda/sim_lib
+Simulation Tool : modelsim-altera
+Simulation Language : verilog
+Simulation Mode : GUI
+Sim Output File :
+Sim SDF file :
+Sim dir : simulation\modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim-Altera software
+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Info: Spawning ModelSim-Altera Simulation software
diff --git a/part_2/ex5/output_files/ex5_top.flow.rpt b/part_2/ex5/output_files/ex5_top.flow.rpt
new file mode 100644
index 0000000..6b65943
--- /dev/null
+++ b/part_2/ex5/output_files/ex5_top.flow.rpt
@@ -0,0 +1,118 @@
+Flow report for ex5_top
+Thu Nov 17 11:24:26 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+-------------------------------------------------+
+; Flow Status ; Successful - Thu Nov 17 11:24:26 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex5_top ;
+; Top-level Entity Name ; counter_8 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 8 ;
+; Total pins ; 10 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 11/17/2016 11:24:17 ;
+; Main task ; Compilation ;
+; Revision Name ; ex5_top ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 260248564268167.147938185604608 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; counter_8 ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; counter_8 ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; counter_8 ; Top ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+; TOP_LEVEL_ENTITY ; counter_8 ; ex5_top ; -- ; -- ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 894 MB ; 00:00:21 ;
+; Total ; 00:00:10 ; -- ; -- ; 00:00:21 ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; Flow OS Summary ;
++----------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++----------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews104a-003 ; Windows 7 ; 6.1 ; x86_64 ;
++----------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5_top
+
+
+
diff --git a/part_2/ex5/output_files/ex5_top.map.rpt b/part_2/ex5/output_files/ex5_top.map.rpt
new file mode 100644
index 0000000..edc31f1
--- /dev/null
+++ b/part_2/ex5/output_files/ex5_top.map.rpt
@@ -0,0 +1,298 @@
+Analysis & Synthesis report for ex5_top
+Thu Nov 17 11:24:26 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Parameter Settings for User Entity Instance: Top-level Entity: |counter_8
+ 10. Post-Synthesis Netlist Statistics for Top Partition
+ 11. Elapsed Time Per Partition
+ 12. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Thu Nov 17 11:24:26 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex5_top ;
+; Top-level Entity Name ; counter_8 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 8 ;
+; Total pins ; 10 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; counter_8 ; ex5_top ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processors 2-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+--------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+--------------------------------+---------+
+; counter_8.v ; yes ; User Verilog HDL File ; C:/VERI/part_2/ex5/counter_8.v ; ;
++----------------------------------+-----------------+------------------------+--------------------------------+---------+
+
+
++-----------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------+
+; Estimate of Logic utilization (ALMs needed) ; 4 ;
+; ; ;
+; Combinational ALUT usage for logic ; 8 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 0 ;
+; -- 5 input functions ; 0 ;
+; -- 4 input functions ; 0 ;
+; -- <=3 input functions ; 8 ;
+; ; ;
+; Dedicated logic registers ; 8 ;
+; ; ;
+; I/O pins ; 10 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; clock~input ;
+; Maximum fan-out ; 8 ;
+; Total fan-out ; 57 ;
+; Average fan-out ; 1.58 ;
++---------------------------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+; |counter_8 ; 8 (8) ; 8 (8) ; 0 ; 0 ; 10 ; 0 ; |counter_8 ; counter_8 ; work ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 8 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 8 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |counter_8 ;
++----------------+-------+--------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------------------+
+; BIT_SZ ; 8 ; Signed Integer ;
++----------------+-------+--------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_ff ; 8 ;
+; ENA ; 8 ;
+; arriav_lcell_comb ; 8 ;
+; arith ; 7 ;
+; 1 data inputs ; 6 ;
+; 2 data inputs ; 1 ;
+; normal ; 1 ;
+; 1 data inputs ; 1 ;
+; boundary_port ; 10 ;
+; ; ;
+; Max LUT depth ; 1.60 ;
+; Average LUT depth ; 1.27 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Thu Nov 17 11:24:16 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5_top
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file counter_8.v
+ Info (12023): Found entity 1: counter_8 File: C:/VERI/part_2/ex5/counter_8.v Line: 4
+Info (12127): Elaborating entity "counter_8" for the top level hierarchy
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 2 input pins
+ Info (21059): Implemented 8 output pins
+ Info (21061): Implemented 8 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 894 megabytes
+ Info: Processing ended: Thu Nov 17 11:24:26 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:22
+
+
diff --git a/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do b/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do
new file mode 100644
index 0000000..98180fe
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/ex5_top_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/VERI/part_2/ex5 {C:/VERI/part_2/ex5/counter_8.v}
+
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
new file mode 100644
index 0000000..245fe11
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -0,0 +1,9 @@
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
+run 100ns \ No newline at end of file
generated by cgit v1.2.3-54-g00ecf (git 2.45.2) at 2024-12-25 07:12:34 +0000