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| author | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
|---|---|---|
| committer | Vasil Zlatanov <v@skozl.com> | 2016-12-12 21:51:10 +0000 |
| commit | 4b6e0102d20d9ab060ce930e4b846c8be446bb06 (patch) | |
| tree | e475eab3716738f2928f0b2063956e9b155f94ab /part_3/ex10a/simulation | |
| download | e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.gz e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.tar.bz2 e2-verilab-4b6e0102d20d9ab060ce930e4b846c8be446bb06.zip | |
public push
Diffstat (limited to 'part_3/ex10a/simulation')
| -rw-r--r-- | part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do | 9 | ||||
| -rw-r--r-- | part_3/ex10a/simulation/modelsim/tb_spi2dac.do | 17 |
2 files changed, 26 insertions, 0 deletions
diff --git a/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do b/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do new file mode 100644 index 0000000..7c53536 --- /dev/null +++ b/part_3/ex10a/simulation/modelsim/ex10a_run_msim_rtl_verilog.do @@ -0,0 +1,9 @@ +transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/VERI/part_3/ex10a {C:/VERI/part_3/ex10a/spi2dac.v}
+
diff --git a/part_3/ex10a/simulation/modelsim/tb_spi2dac.do b/part_3/ex10a/simulation/modelsim/tb_spi2dac.do new file mode 100644 index 0000000..b12a7d7 --- /dev/null +++ b/part_3/ex10a/simulation/modelsim/tb_spi2dac.do @@ -0,0 +1,17 @@ +add wave -position end sysclk +add wave -position end -hexadecimal data_in +add wave -position end load +add wave -position end dac_sdi +add wave -position end dac_cs +add wave -position end dac_sck +add wave -position end dac_ld +force sysclk 1 0, 0 10ns -r 20ns +force data_in 10'h23b +force load 0 +run 200ns +force load 1 +run 400ns +force load 0 +run 20us + + |